1850 search results - page 48 / 370 » Power and performance optimization at the system level |
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
LCPC
2004
Springer
15 years 3 months ago
2004
Springer
Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor a...
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
FTEDA
2006
14 years 9 months ago
2006
As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing process...
OSDI
2002
ACM
15 years 10 months ago
2002
ACM
Combining high performance with low power consumption is becoming one of the primary objectives of processor designs. Instead of relying just on sleep mode for conserving power, a...