1850 search results - page 4 / 370 » Power and performance optimization at the system level |
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
ISLPED
1999
ACM
15 years 1 months ago
1999
ACM
-- The goal of a dynamic power management policy is to reduce the power consumption of an electronic system by putting system components into different states, each representing ce...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
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Voted
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
EUROMICRO
2000
IEEE
15 years 2 months ago
2000
IEEE
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...