1850 search results - page 5 / 370 » Power and performance optimization at the system level |
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
DATE
2007
IEEE
15 years 3 months ago
2007
IEEE
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
ICC
2007
IEEE
15 years 3 months ago
2007
IEEE
Ultra wideband (UWB) systems are currently an important wireless infrastructure for efficient shortrange communications. To improve the system efficiency while guaranteeing the ra...
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
IROS
2006
IEEE
15 years 3 months ago
2006
IEEE
In this investigation a robotic system’s dynamic performance is optimized for high reliability under uncertainty. The dynamic capability equations allow designers to predict the...