1850 search results - page 72 / 370 » Power and performance optimization at the system level |
107
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IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
WCE
2007
14 years 11 months ago
2007
— In this paper a new approach to optimize nuclear power plant designs based on global risk reduction are described. In design the focus is on as components quality as redundancy...
ICS
2003
Tsinghua U.
15 years 3 months ago
2003
Tsinghua U.
—The ever-increasing computational power of contemporary microprocessors reduces the execution time spent on arithmetic computations (i.e., the computations not involving slow me...
113
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DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
IISWC
2009
IEEE
15 years 4 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...