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» Power and performance optimization at the system level
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ISPD
2005
ACM
116views Hardware» more  ISPD 2005»
15 years 3 months ago
A fast algorithm for power grid design
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
Jaskirat Singh, Sachin S. Sapatnekar
VLSID
2005
IEEE
129views VLSI» more  VLSID 2005»
15 years 10 months ago
A RISC Hardware Platform for Low Power Java
Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of ...
Paul Capewell, Ian Watson
GLOBECOM
2007
IEEE
15 years 4 months ago
Outage Behavior of Quasi-Static Fading Channels with Partial Power Control and Noisy Feedback
Abstract— We investigate the outage behavior of multipleantenna slowly fading channels with resolution constrained feedback and partial power control. A fixed-rate communication...
Siavash Ekbatani, Farzad Etemadi, Hamid Jafarkhani
IEEEINTERACT
2003
IEEE
15 years 3 months ago
High Performance Code Generation through Lazy Activation Records
For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to m...
Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth ...
EENERGY
2010
15 years 1 months ago
Energy saving and network performance: a trade-off approach
Power consumption of the Information and Communication Technology sector (ICT) has recently become a key challenge. In particular, actions to improve energy-efficiency of Internet...
Carla Panarello, Alfio Lombardo, Giovanni Schembra...