Sciweavers

1850 search results - page 92 / 370
» Power and performance optimization at the system level
Sort
View
ISVLSI
2006
IEEE
126views VLSI» more  ISVLSI 2006»
15 years 3 months ago
QUKU: A Two-Level Reconfigurable Architecture
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker
TWC
2008
177views more  TWC 2008»
14 years 9 months ago
Generalized Design of Multi-User MIMO Precoding Matrices
In this paper we introduce a novel linear precoding technique. The approach used for the design of the precoding matrix is general and the resulting algorithm can address several o...
Veljko Stankovic, Martin Haardt
CORR
2007
Springer
108views Education» more  CORR 2007»
14 years 9 months ago
Error Probability Analysis of Peaky Signaling over Fading Channels
Abstract— In this paper, the performance of signaling strategies with high peak-to-average power ratio is analyzed in both coherent and noncoherent fading channels Two recently p...
Mustafa Cenk Gursoy
FORMATS
2009
Springer
15 years 4 months ago
Exploiting Timed Automata for Conformance Testing of Power Measurements
For software development, testing is still the primary choice for investigating the correctness of a system. Automated testing is of utmost importance to support continuous integra...
Matthias Woehrle, Kai Lampka, Lothar Thiele
DAC
2006
ACM
15 years 10 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...