Sciweavers

157 search results - page 13 / 32
» Power and performance tradeoffs using various caching strate...
Sort
View
LCTRTS
2007
Springer
15 years 4 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
HPCA
2009
IEEE
15 years 10 months ago
Hardware-software integrated approaches to defend against software cache-based side channel attacks
Software cache-based side channel attacks present serious threats to modern computer systems. Using caches as a side channel, these attacks are able to derive secret keys used in ...
Jingfei Kong, Onur Aciiçmez, Jean-Pierre Se...
DATE
2005
IEEE
133views Hardware» more  DATE 2005»
15 years 3 months ago
Locality-Aware Process Scheduling for Embedded MPSoCs
Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work th...
Mahmut T. Kandemir, Guilin Chen
EUC
2004
Springer
15 years 3 months ago
Implementing Cooperative Caching in Distributed Streaming Media Server Clusters
Abstract. In distributed streaming media server clusters, by adopting cooperative caching (CC) technique, the free memory of all the servers can be combined to form a bigger, logic...
Tiecheng Gu, Baoliu Ye, Minyi Guo, Daoxu Chen
EUROPAR
2003
Springer
15 years 3 months ago
Exploiting On-Chip Data Transfers for Improving Performance of Chip-Scale Multiprocessors
As compared to a complex single processor based system, on-chip multiprocessors are less complex, more power efficient, and easier to test and validate. In this work, we focus on a...
Guangyu Chen, Mahmut T. Kandemir, Alok N. Choudhar...