157 search results - page 8 / 32 » Power and performance tradeoffs using various caching strate... |
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
This paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. More precisely, we introduce an analytical approach based on ...
DAC
2003
ACM
15 years 11 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
GLOBECOM
2007
IEEE
15 years 4 months ago
2007
IEEE
—Comprehensive performance analysis of the unordered V-BLAST algorithm with various power allocation strategies is presented, which makes use of analytical tools and resorts to M...
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...