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» Power emulation: a new paradigm for power estimation
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VLSID
2005
IEEE
224views VLSI» more  VLSID 2005»
15 years 10 months ago
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
DAC
2007
ACM
15 years 10 months ago
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...
Lei Cheng, Deming Chen, Martin D. F. Wong
SOCC
2008
IEEE
151views Education» more  SOCC 2008»
15 years 4 months ago
Failure analysis for ultra low power nano-CMOS SRAM under process variations
— Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
PPDP
1999
Springer
15 years 1 months ago
Distributed Programming in a Multi-Paradigm Declarative Language
Curry is a multi-paradigm declarative language covering functional, logic, and concurrent programming paradigms. Curry’s operational semantics is based on lazy reduction of expre...
Michael Hanus
100
Voted
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
14 years 7 months ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai