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» Power emulation: a new paradigm for power estimation
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ICASSP
2011
IEEE
14 years 1 months ago
Fast estimation of the state of the power grid using synchronized phasor measurements
—Both the communication limitation and the measurement properties based algorithm become the bottleneck of enhancing the traditional power system state estimation speed. The avai...
Tao Yang, Anjan Bose
ISLPED
1997
ACM
130views Hardware» more  ISLPED 1997»
15 years 1 months ago
K2: an estimator for peak sustainable power of VLSI circuits
New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as wel...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
15 years 4 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
EUROPAR
2007
Springer
15 years 3 months ago
Virtualization Techniques in Network Emulation Systems
The continuous increase of computational power has made viable the implementation of more and more sophisticated virtualization techniques. The use of virtualization in cluster env...
Roberto Canonico, Pasquale Di Gennaro, Vittorio Ma...
DAC
2002
ACM
15 years 10 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan