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GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
15 years 5 months ago
Mixing ATPG and property checking for testing HW/SW interfaces
A critical part of the design of HW/SW systems concerns the definition of the HW/SW interface. Such interfaces do not directly map a functionality of the system description, but ...
Alessandro Fin, Franco Fummi, Graziano Pravadelli
ISCAS
2007
IEEE
149views Hardware» more  ISCAS 2007»
15 years 6 months ago
Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition
— Many application-specific wireless sensor network (WSN) systems require small size and low power features due to their limited resources, and their use in distributed, wireles...
Chung-Ching Shen, Roni Kupershtok, Bo Yang, Felice...
IPPS
2008
IEEE
15 years 6 months ago
Towards a decentralized architecture for optimization
We introduce a generic framework for the distributed execution of combinatorial optimization tasks. Instead of relying on custom hardware (like dedicated parallel machines or clus...
Marco Biazzini, Mauro Brunato, Alberto Montresor
ASPDAC
1999
ACM
157views Hardware» more  ASPDAC 1999»
15 years 4 months ago
A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph Optimization
: This paper presents a genetic algorithm based approach for algebraic optimization of behavioral system specifications. We introduce a chromosomal representation of data-flow gr...
Birger Landwehr
ASPDAC
1999
ACM
149views Hardware» more  ASPDAC 1999»
15 years 4 months ago
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...
Jinsong Hou, Zeyi Wang, Xianlong Hong