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ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 3 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
15 years 5 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
ISCAS
1994
IEEE
124views Hardware» more  ISCAS 1994»
15 years 3 months ago
Efficient Gabor Filter Design Using Rician Output Statistics
Gabor filters have been applied sucessfully to a broad range of multidimensional signal processing and image processing tasks. The present paper considers the design of a single f...
Thomas P. Weldon, William E. Higgins, Dennis F. Du...
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
15 years 5 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
DATE
1999
IEEE
172views Hardware» more  DATE 1999»
15 years 4 months ago
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
Olivier Pasquier, Jean Paul Calvez