Sciweavers

95 search results - page 15 / 19
» Power estimation for cycle-accurate functional descriptions ...
Sort
View
57
Voted
ASAP
2007
IEEE
109views Hardware» more  ASAP 2007»
14 years 11 months ago
Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming!
This paper explores the reliability of three different minimum fan-in majority gates full adder (FA) designs, and compares them to the performance of a standard XOR-based FA. The ...
Walid Ibrahim, Valeriu Beiu
ICCD
2004
IEEE
128views Hardware» more  ICCD 2004»
15 years 6 months ago
Static Transition Probability Analysis Under Uncertainty
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
Siddharth Garg, Siddharth Tata, Ravishankar Arunac...
SAT
2009
Springer
126views Hardware» more  SAT 2009»
15 years 4 months ago
Extending SAT Solvers to Cryptographic Problems
Cryptography ensures the confidentiality and authenticity of information but often relies on unproven assumptions. SAT solvers are a powerful tool to test the hardness of certain ...
Mate Soos, Karsten Nohl, Claude Castelluccia
GECCO
2004
Springer
148views Optimization» more  GECCO 2004»
15 years 2 months ago
A Multi-objective Approach to Configuring Embedded System Architectures
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware un...
James Northern III, Michael A. Shanblatt
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
15 years 4 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie