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DATE
1999
IEEE
118views Hardware» more  DATE 1999»
15 years 1 months ago
Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
Michael S. Hsiao
87
Voted
ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
15 years 6 months ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
ICES
2010
Springer
106views Hardware» more  ICES 2010»
14 years 7 months ago
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application
Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...
Jaroslav Skarvada, Zdenek Kotásek, Josef St...
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
15 years 2 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft
ISLPED
1996
ACM
110views Hardware» more  ISLPED 1996»
15 years 1 months ago
Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power ba...
Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang