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123
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VLSID
1999
IEEE
139views VLSI» more  VLSID 1999»
15 years 1 months ago
Processor Modeling for Hardware Software Codesign
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
V. Rajesh, Rajat Moona
74
Voted
ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
15 years 6 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal
DAC
1999
ACM
15 years 1 months ago
Common-Case Computation: A High-Level Technique for Power and Performance Optimization
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed ...
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S...
79
Voted
IJCSS
2007
133views more  IJCSS 2007»
14 years 9 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja
69
Voted
DATE
1999
IEEE
86views Hardware» more  DATE 1999»
15 years 1 months ago
Glitch Power Minimization by Gate Freezing
This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...