95 search results - page 6 / 19 » Power estimation for cycle-accurate functional descriptions ... |
ISCAS
2008
IEEE
15 years 3 months ago
2008
IEEE
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
86
Voted
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
In modern circuit design, it is difficult to provide reliable parametric yield prediction since the real distribution of process data is hard to measure. Most existing approaches ...
ATS
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...
91
Voted
ISLPED
2007
ACM
14 years 11 months ago
2007
ACM
RTL power macromodeling is a mature research topic with a variety of equation and table-based approaches. Despite its maturity, macromodeling is not yet widely accepted as an indu...
85
Voted
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...