Sciweavers

71 search results - page 2 / 15
» Power ground supply network optimization for power-gating
Sort
View
DATE
2010
IEEE
166views Hardware» more  DATE 2010»
13 years 11 months ago
From transistors to MEMS: Throughput-aware power gating in CMOS circuits
—In this paper we study the effectiveness of two power gating methods – transistor switches and MEMS switches – in reducing the power consumption of a design with a certain t...
Michael B. Henry, Leyla Nazhandali
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 10 months ago
Thermal and Power Integrity Based Power/Ground Networks Optimization
With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects...
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Pin...
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific t...
Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun ...
GLVLSI
2010
IEEE
119views VLSI» more  GLVLSI 2010»
13 years 11 months ago
Line width optimization for interdigitated power/ground networks
Higher operating frequencies have increased the importance of inductance in power and ground networks. The effective inductance of the power and ground network can be reduced with...
Renatas Jakushokas, Eby G. Friedman
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
13 years 11 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...