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» Power management in external memory using PA-CDRAM
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87
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ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
15 years 3 months ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
88
Voted
IEEEPACT
2006
IEEE
15 years 3 months ago
Compiling for stream processing
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
Abhishek Das, William J. Dally, Peter R. Mattson
FCCM
2009
IEEE
123views VLSI» more  FCCM 2009»
15 years 1 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
Hoang Le, Viktor K. Prasanna
ASPDAC
2009
ACM
110views Hardware» more  ASPDAC 2009»
15 years 4 months ago
A software solution for dynamic stack management on scratch pad memory
Abstract— In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. Howe...
Arun Kannan, Aviral Shrivastava, Amit Pabalkar, Jo...
95
Voted
TPDS
2008
101views more  TPDS 2008»
14 years 9 months ago
An Energy-Oriented Evaluation of Buffer Cache Algorithms Using Parallel I/O Workloads
Power consumption is an important issue for cluster supercomputers as it directly affects running cost and cooling requirements. This paper investigates the memory energy efficienc...
Jianhui Yue, Yifeng Zhu, Zhao Cai