318 search results - page 10 / 64 » Power minimization for dynamic PLAs |
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INFOCOM
2012
IEEE
13 years 2 days ago
2012
IEEE
—This paper considers a component-level deceleration technique in BS operation, called speed-scaling, that is more conservative than entirely shutting down BSs, yet can conserve ...
CODES
2003
IEEE
15 years 2 months ago
2003
IEEE
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
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ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
Abstract— The mixed-signal processor performs digital vectormatrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell ...
HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
CODES
2001
IEEE
15 years 1 months ago
2001
IEEE
Power consumption is an important design parameter for embedded and portable systems. Software-controlled (or dynamic) power management (DPM) has recently emerged as an attractive...