318 search results - page 11 / 64 » Power minimization for dynamic PLAs |
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INFOCOM
2010
IEEE
14 years 8 months ago
2010
IEEE
Abstract—We consider the power control problem in a timeslotted wireless channel, shared by a finite number of mobiles that transmit to a common base station. The channel betwee...
98
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MSN
2005
Springer
15 years 3 months ago
2005
Springer
In the area of wireless mobile communication, minimizing energy consumption as well as maximizing data throughput in medium access control (MAC) layer is a very important research ...
81
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PATMOS
2005
Springer
15 years 3 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
INFOCOM
2011
IEEE
14 years 1 months ago
2011
IEEE
—Heterogeneous wireless networks employ varying degrees of network coverage using power control in a multi-tier configuration, where low-power femtocells are used to enhance per...