318 search results - page 14 / 64 » Power minimization for dynamic PLAs |
HPCA
2001
IEEE
15 years 10 months ago
2001
IEEE
With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and po...
ICRA
2006
IEEE
15 years 3 months ago
2006
IEEE
— In this paper, we propose a power assist system that amplifies sinusoidal human’s torque and attains minimization of control input requirement using an impedance control and...
CORR
2011
Springer
14 years 4 months ago
2011
Springer
—Cloud providers, like Amazon, offer their data centers’ computational and storage capacities for lease to paying customers. High electricity consumption, associated with runni...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
TC
2008
14 years 9 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...