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» Power minimization for dynamic PLAs
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EVOW
2011
Springer
14 years 1 months ago
Two Iterative Metaheuristic Approaches to Dynamic Memory Allocation for Embedded Systems
Abstract. Electronic embedded systems designers aim at finding a tradeoff between cost and power consumption. As cache memory management has been shown to have a significant imp...
María Soto, André Rossi, Marc Sevaux
ISQED
2006
IEEE
176views Hardware» more  ISQED 2006»
15 years 3 months ago
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
Zhiyu Liu, Volkan Kursun
MONET
2011
14 years 4 months ago
iDSRT: Integrated Dynamic Soft Real-time Architecture for Critical Infrastructure Data Delivery over WLAN
Critical Infrastructures (CIs) such as the Power Grid play an important role in our lives. Of all important aspects of CIs, real-time data delivery is the most important one becaus...
Hoang Viet Nguyen, Raoul Rivas, Klara Nahrstedt
TSMC
2010
14 years 4 months ago
Multiobjective Optimization of Temporal Processes
Abstract--This paper presents a dynamic predictiveoptimization framework of a nonlinear temporal process. Datamining (DM) and evolutionary strategy algorithms are integrated in the...
Zhe Song, Andrew Kusiak
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
15 years 1 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...