Sciweavers

318 search results - page 27 / 64
» Power minimization for dynamic PLAs
Sort
View
ISCAS
2005
IEEE
140views Hardware» more  ISCAS 2005»
15 years 3 months ago
Low energy asynchronous architectures
: Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and d...
Ilya Obridko, Ran Ginosar
DAC
2006
ACM
15 years 10 months ago
High-level power management of embedded systems with application-specific energy cost functions
Most existing dynamic voltage scaling (DVS) schemes for multiple tasks assume an energy cost function (energy consumption versus execution time) that is independent of the task ch...
Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti...
GLOBECOM
2007
IEEE
14 years 11 months ago
The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation
: The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turne...
Min Li, Bruno Bougard, Eduardo Lopez-Estraviz, And...
PLDI
2003
ACM
15 years 3 months ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
FAST
2010
15 years 1 days ago
SRCMap: Energy Proportional Storage Using Dynamic Consolidation
We investigate the problem of creating an energy proportional storage system through power-aware dynamic storage consolidation. Our proposal, Sample-ReplicateConsolidate Mapping (...
Akshat Verma, Ricardo Koller, Luis Useche, Raju Ra...