Sciweavers

318 search results - page 33 / 64
» Power minimization for dynamic PLAs
Sort
View
ICPP
2002
IEEE
15 years 4 months ago
Software Caching using Dynamic Binary Rewriting for Embedded Devices
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...
Chad Huneycutt, Joshua B. Fryman, Kenneth M. Macke...
105
Voted
WSC
2000
15 years 15 days ago
Cost/benefit analysis of interval jumping in power-control simulation
Computation of power control calculations is one of the most time-consuming aspects of simulating wireless communication systems. These calculations are critical to understanding ...
David M. Nicol, L. Felipe Perrone
ECCV
2010
Springer
15 years 8 days ago
Robust and Fast Collaborative Tracking with Two Stage Sparse Optimization
Abstract. The sparse representation has been widely used in many areas and utilized for visual tracking. Tracking with sparse representation is formulated as searching for samples ...
Baiyang Liu, Lin Yang, Junzhou Huang, Peter Meer, ...
IJPP
2011
107views more  IJPP 2011»
14 years 5 months ago
Parallel Iterator for Parallelizing Object-Oriented Applications
With the advent of multi-core processors, desktop application developers must finally face parallel computing and its challenges. A large portion of the computational load in a p...
Nasser Giacaman, Oliver Sinnen
EMSOFT
2004
Springer
15 years 4 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande