318 search results - page 41 / 64 » Power minimization for dynamic PLAs |
82
Voted
DAC
2008
ACM
15 years 10 months ago
2008
ACM
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
ASPDAC
2000
ACM
15 years 2 months ago
2000
ACM
Simulated annealing has been one of the most popular stochastic optimization methods used in the VLSI CAD field in the past two decades for handling NP-hard optimization problems...
107
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CGO
2005
IEEE
15 years 3 months ago
2005
IEEE
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...
89
Voted
ISLPED
2004
ACM
15 years 3 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...