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» Power minimization for dynamic PLAs
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DATE
2006
IEEE
87views Hardware» more  DATE 2006»
15 years 3 months ago
Thermal resilient bounded-skew clock tree optimization methodology
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
Ashutosh Chakraborty, Prassanna Sithambaram, Karth...
79
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
ICSE
1999
IEEE-ACM
15 years 1 months ago
Information Survivability Control Systems
We address the dependence of critical infrastructures— including electric power, telecommunications, finance and transportation—on vulnerable information systems. Our approach...
Kevin J. Sullivan, John C. Knight, Xing Du, Steve ...
JELIA
1994
Springer
15 years 1 months ago
Temporal Theories of Reasoning
: In this paper we describe a general way of formalizing reasoning behaviour. Such a behaviour may be described by all the patterns which are valid for the behaviour. A pattern can...
Joeri Engelfriet, Jan Treur
76
Voted
ICPR
2010
IEEE
15 years 28 days ago
A Hypothesis Testing Approach for Fluorescent Blob Identification
Template matching is a common approach for identifying fluorescent objects within a biological image. But how to decide a threshold value for the purpose of justifying the goodness...
Le-Shin Wu, Sidney Shaw