318 search results - page 8 / 64 » Power minimization for dynamic PLAs |
101
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ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
69
Voted
IPPS
2003
IEEE
15 years 2 months ago
2003
IEEE
Power management is critical to power-constrained real-time systems. In this paper, we present a dynamic power management algorithm for real-time heterogeneous systems. Unlike oth...
108
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SLIP
2004
ACM
15 years 3 months ago
2004
ACM
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
74
Voted
FPGA
2007
ACM
15 years 3 months ago
2007
ACM
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...