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» Power minimization using control generated clocks
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DSD
2004
IEEE
104views Hardware» more  DSD 2004»
15 years 1 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...
CODES
2001
IEEE
15 years 1 months ago
Retargetable compilation for low power
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
Wen-Tsong Shiue
IWSOC
2003
IEEE
99views Hardware» more  IWSOC 2003»
15 years 3 months ago
Template Generation and Selection Algorithms
The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extra...
Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Pa...
ASMTA
2010
Springer
192views Mathematics» more  ASMTA 2010»
14 years 7 months ago
Packet Loss Minimization in Load-Balancing Switch
Due to the overall growing demand on the network resources and tight restrictions on the power consumption, the requirements to the long-term scalability, cost and performance capa...
Yury Audzevich, Levente Bodrog, Yoram Ofek, Mikl&o...
CDC
2010
IEEE
161views Control Systems» more  CDC 2010»
14 years 4 months ago
Circadian system modeling and phase control
Circadian rhythms are biological processes found in all living organisms, from plants to insects to mammals that repeat with a period close to, but not exactly, 24 hours. In the ab...
Jiaxiang Zhang, Andrew Bierman, John T. Wen, Agung...