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DAC
2005
ACM
16 years 12 days ago
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
King Ho Tam, Lei He
TVLSI
2010
14 years 6 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
INFOCOM
2003
IEEE
15 years 4 months ago
Power Constrained and Delay Optimal Policies for Scheduling Transmission over a Fading Channel
ACT We consider an optimal power and rate scheduling problem for a single user transmitting to a base station on a fading wireless link with the objective of minimizing the mean de...
Munish Goyal, Anurag Kumar, Vinod Sharma
TCAD
2010
116views more  TCAD 2010»
14 years 6 months ago
MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...
Anand Rajaram, David Z. Pan
INFOCOM
2010
IEEE
14 years 10 months ago
Multicast Scheduling with Cooperation and Network Coding in Cognitive Radio Networks
—Cognitive Radio Networks (CRNs) have recently emerged as a promising technology to improve spectrum utilization by allowing secondary users to dynamically access idle primary ch...
Jin Jin, Hong Xu, Baochun Li