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» Power optimization and management in embedded systems
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IEEEINTERACT
2003
IEEE
15 years 4 months ago
High Performance Code Generation through Lazy Activation Records
For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to m...
Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth ...
90
Voted
EMSOFT
2007
Springer
15 years 5 months ago
Block recycling schemes and their cost-based optimization in nand flash memory based storage system
Flash memory has many merits such as light weight, shock resistance, and low power consumption, but also has limitations like the erase-before-write property. To overcome such lim...
Jongmin Lee, Sunghoon Kim, Hunki Kwon, Choulseung ...
TCAD
2008
114views more  TCAD 2008»
14 years 10 months ago
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...
EOR
2006
178views more  EOR 2006»
14 years 11 months ago
A fuzzy optimization model for QFD planning process using analytic network approach
In both the quality improvement and the design of a product, the engineering characteristics affecting product performance are primarily identified and improved to optimize custom...
Cengiz Kahraman, Tijen Ertay, Gülçin B...
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
15 years 3 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...