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ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
Weiping Shi, Zhuo Li, Charles J. Alpert
ASPDAC
2008
ACM
93views Hardware» more  ASPDAC 2008»
15 years 6 months ago
Scheduling with integer time budgeting for low-power optimization
In this paper we present a mathematical programming formulation of the integer time budgeting problem for directed acyclic graphs. In particular, we formally prove that our constr...
Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason C...
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
15 years 11 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 11 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
ICCSA
2003
Springer
15 years 10 months ago
Optimization in the Context of Active Control of Sound
A problem of eliminating the unwanted time-harmonic noise on a predetermined region of interest is solved by active means, i.e., by introducing the additional sources of sound, cal...
Josip Loncaric, Semyon Tsynkov