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DAC
2002
ACM
16 years 5 months ago
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...
Andrea Bona, Mariagiovanna Sami, Donatella Sciuto,...
IESS
2007
Springer
116views Hardware» more  IESS 2007»
15 years 10 months ago
Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes
This work investigates the use of reconfigurable devices as computing platform for self-organizing embedded systems. Those usually consist of a set of distributed, autonomous node...
Dominik Murr, Felix Mühlbauer, Falko Dressler...
VLDB
2007
ACM
204views Database» more  VLDB 2007»
15 years 10 months ago
Optimization of Frequent Itemset Mining on Multiple-Core Processor
Multi-core processors are proliferated across different domains in recent years. In this paper, we study the performance of frequent pattern mining on a modern multi-core machine....
Eric Li, Li Liu
DATE
2006
IEEE
87views Hardware» more  DATE 2006»
15 years 10 months ago
Thermal resilient bounded-skew clock tree optimization methodology
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
Ashutosh Chakraborty, Prassanna Sithambaram, Karth...
ICPP
2002
IEEE
15 years 9 months ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha