390 search results - page 26 / 78 » Power system on a chip (PSoC) |
ISCA
2009
IEEE
15 years 6 months ago
2009
IEEE
Dynamic voltage and frequency scaling (DVFS) is a commonly-used powermanagement scheme that dynamically adjusts power and performance to the time-varying needs of running programs...
101
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ICCAD
2003
IEEE
15 years 8 months ago
2003
IEEE
Emerging VLSI technologies and platforms are giving rise to systems with inherently high potential for runtime failure. Such failures range from intermittent electrical and mechan...
ISPD
2005
ACM
15 years 5 months ago
2005
ACM
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
158
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ISCA
2011
IEEE
14 years 3 months ago
2011
IEEE
Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to wh...
CODES
2006
IEEE
15 years 5 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...