Sciweavers

390 search results - page 33 / 78
» Power system on a chip (PSoC)
Sort
View
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
15 years 6 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
ISCAS
2005
IEEE
173views Hardware» more  ISCAS 2005»
15 years 5 months ago
CMOS contact imager for monitoring cultured cells
— There is a growing interest in developing low cost, low power, highly integrated biosensor systems to characterize individual cells for applications such as cell analysis, drug...
Honghao Ji, Pamela Abshire, M. Urdaneta, Elisabeth...
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
16 years 4 days ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
HOTI
2005
IEEE
15 years 5 months ago
High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme
A partitioned TCAM-based search engine is presented that increases packet forwarding rate multiple times over traditional TCAMs. The model works for IPv4 and IPv6 packet forwardin...
Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Pa...
101
Voted
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
15 years 5 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu