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» Power system on a chip (PSoC)
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ISLPED
2003
ACM
80views Hardware» more  ISLPED 2003»
15 years 5 months ago
Level conversion for dual-supply systems
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic
VLSID
2004
IEEE
85views VLSI» more  VLSID 2004»
16 years 5 days ago
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System
A key component of the Data-Intensive Architecture (DIVA) is the Processing-In-Memory (PIM) Routing Component (PiRC) that is responsible for efficient communication between PIM ch...
Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Drape...
DDECS
2009
IEEE
146views Hardware» more  DDECS 2009»
15 years 3 months ago
Enhanced LEON3 core for superscalar processing
Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-o...
Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A....
ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
15 years 3 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...
112
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CASES
2007
ACM
15 years 3 months ago
Performance optimal processor throttling under thermal constraints
We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature co...
Ravishankar Rao, Sarma B. K. Vrudhula