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» Power system on a chip (PSoC)
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ASPDAC
2004
ACM
132views Hardware» more  ASPDAC 2004»
15 years 5 months ago
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications
– A low-power graphics LSI is designed and implemented for mobile multimedia applications. The LSI contains a 32bit RISC processor with enhanced MAC, a 3D rendering engine, progr...
Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun S...
DAC
2003
ACM
16 years 23 days ago
A low-energy chip-set for wireless intercom
A low power wireless intercom system is designed and implemented. Two fully-operational ASICs, integrating custom and commercial IP, implement the entire digital portion of the pr...
M. Josie Ammer, Michael Sheets, Tufan C. Karalar, ...
VLSID
2000
IEEE
79views VLSI» more  VLSID 2000»
15 years 4 months ago
Inductive Noise Reduction at the Architectural Level
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
CASES
2008
ACM
15 years 1 months ago
Active control and digital rights management of integrated circuit IP cores
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
Yousra Alkabani, Farinaz Koushanfar
CODES
2008
IEEE
15 years 1 months ago
Design and defect tolerance beyond CMOS
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. ...