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IEEEHPCS
2010
14 years 9 months ago
Reducing memory requirements of stream programs by graph transformations
Stream languages explicitly describe fork-join parallelism and pipelines, offering a powerful programming model for many-core Multi-Processor Systems on Chip (MPSoC). In an embedd...
Pablo de Oliveira Castro, Stéphane Louise, ...
DATE
2009
IEEE
153views Hardware» more  DATE 2009»
15 years 6 months ago
TRAM: A tool for Temperature and Reliability Aware Memory Design
— Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system’s power dissipation, area and reliability. In th...
Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurd...
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 4 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
DATE
2008
IEEE
99views Hardware» more  DATE 2008»
15 years 6 months ago
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures
As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can serious...
Fabrizio Mulas, Michele Pittau, Marco Buttu, Salva...
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 4 months ago
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
Rudy Beraha, Isask'har Walter, Israel Cidon, Avino...