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VLSID
2002
IEEE
159views VLSI» more  VLSID 2002»
16 years 1 months ago
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...
ENTCS
2006
163views more  ENTCS 2006»
15 years 1 months ago
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC
In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchr...
Frank K. Gürkaynak, Stephan Oetiker, Hubert K...
100
Voted
DAC
2009
ACM
16 years 2 months ago
ILP-based pin-count aware design methodology for microfluidic biochips
Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a k...
Cliff Chiung-Yu Lin, Yao-Wen Chang
DAC
2002
ACM
16 years 2 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou
CF
2008
ACM
15 years 3 months ago
A modular 3d processor for flexible product design and technology migration
The current methodology used in mass-market processor design is to create a single base microarchitecture (e.g., Intel's "Core"or AMD's"K8") that is ...
Gabriel H. Loh