Sciweavers

1145 search results - page 107 / 229
» Power-Driven Design Partitioning
Sort
View
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
16 years 1 months ago
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
Jens Bieger, Sorin A. Huss, Michael Jung, Stephan ...
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
15 years 7 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
MOBICOM
2012
ACM
13 years 4 months ago
Argos: practical many-antenna base stations
Multi-user multiple-input multiple-output theory predicts manyfold capacity gains by leveraging many antennas on wireless base stations to serve multiple clients simultaneously th...
Clayton Shepard, Hang Yu, Narendra Anand, Erran Li...
ICCAD
2005
IEEE
125views Hardware» more  ICCAD 2005»
15 years 10 months ago
Robust mixed-size placement under tight white-space constraints
A novel and very simple correct-by-construction top-down methodology for high-utilization mixed-size placement is presented. The PolarBear algorithm combines recursive cutsize-dri...
Jason Cong, Michail Romesis, Joseph R. Shinnerl
93
Voted
DAC
2009
ACM
16 years 2 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...