1145 search results - page 110 / 229 » Power-Driven Design Partitioning |
112
Voted
SBACPAD
2007
IEEE
15 years 7 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
105
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DAC
2004
ACM
15 years 7 months ago
2004
ACM
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
117
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IWSOC
2003
IEEE
15 years 6 months ago
2003
IEEE
— Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip. Sharing IP blocks in such a competitive market poses significant h...
113
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ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
IP blocks and large macro cells are increasingly prevalent in physical design, actually causing an increase in the available free space for the dust logic. We observe that top-dow...
120
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FUN
2007
Springer
15 years 5 months ago
2007
Springer
Architectures for optical processors designed to solve bounded instances of NP-Complete problems are suggested. One approach mimics the traveling salesman by traveling beams that ...