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ISSS
2000
IEEE
290views Hardware» more  ISSS 2000»
15 years 6 months ago
Mapping Array Communication onto FIFO Communication - Towards an Implementation
In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation ...
Jeffrey Kang, Albert van der Werf, Paul E. R. Lipp...
96
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FPL
2006
Springer
115views Hardware» more  FPL 2006»
15 years 5 months ago
Executing Hardware as Parallel Software for Picoblaze Networks
Multi-processor architectures have gained interest recently because of their ability to exploit programmable silicon parallelism at acceptable power-efficiency figures. Despite th...
Pengyuan Yu, Patrick Schaumont
FPL
2000
Springer
130views Hardware» more  FPL 2000»
15 years 5 months ago
Area-Optimized Technology Mapping for Hybrid FPGAs
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
Srini Krishnamoorthy, Sriram Swaminathan, Russell ...
CSREAESA
2006
15 years 2 months ago
Power Optimization of Interconnection Networks for Transport Triggered Architecture
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
Xue-mi Zhao, Zhiying Wang
CASCON
1996
102views Education» more  CASCON 1996»
15 years 2 months ago
Availability management of distributed programs and services
Modern distributed applications pose increasing demands for high availability, automatic management, and dynamic con guration of their software systems. This paper presents the ar...
Markus Endler