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ISPD
2010
ACM
207views Hardware» more  ISPD 2010»
15 years 8 months ago
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this paper we present FOARS, ...
Gaurav Ajwani, Chris Chu, Wai-Kei Mak
INFOCOM
2009
IEEE
15 years 8 months ago
Capacity Provisioning a Valiant Load-Balanced Network
—Valiant load balancing (VLB), also called two-stage load balancing, is gaining popularity as a routing scheme that can serve arbitrary traffic matrices. To date, VLB network de...
Andrew R. Curtis, Alejandro López-Ortiz
DATE
2008
IEEE
89views Hardware» more  DATE 2008»
15 years 8 months ago
Symbolic Reliability Analysis and Optimization of ECU Networks
Increasing reliability at a minimum amount of extra cost is a major challenge in todays ECU network design. Considering reliability as an objective already in early design phases ...
Michael Glaß, Martin Lukasiewycz, Felix Reim...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
15 years 7 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
GLVLSI
2006
IEEE
142views VLSI» more  GLVLSI 2006»
15 years 7 months ago
Dynamic instruction schedulers in a 3-dimensional integration technology
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
Kiran Puttaswamy, Gabriel H. Loh