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» Power-Driven Design Partitioning
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WISER
2004
ACM
15 years 7 months ago
Hardware/software co-design for power system test development
Many hardware/software co-design models have been proposed [7, 2, 5, 6] that attempt to address problems in the hardware/software interface, in partitioning the system between har...
Austin Armbruster, Matt Ryan, Xiaoqing Frank Liu, ...
PATMOS
2004
Springer
15 years 6 months ago
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
Geoff V. Merrett, Bashir M. Al-Hashimi
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
15 years 6 months ago
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
Wonjoon Choi, Kia Bazargan
DATE
2010
IEEE
111views Hardware» more  DATE 2010»
15 years 6 months ago
Evaluation of runtime task mapping heuristics with rSesame - a case study
Abstract—rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to ex...
Kamana Sigdel, Mark Thompson, Carlo Galuzzi, Andy ...
ICCAD
1998
IEEE
120views Hardware» more  ICCAD 1998»
15 years 5 months ago
Communication synthesis for distributed embedded systems
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
Ross B. Ortega, Gaetano Borriello