2 search results - page 1 / 1 » Power-Efficient Spilling Techniques for Chip Multiprocessors |
79
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EUROPAR
2010
Springer
14 years 9 months ago
2010
Springer
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
110
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CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...