426 search results - page 12 / 86 » Power-Sensitive Multithreaded Architecture |
178
Voted
PDP
2002
IEEE
15 years 11 months ago
2002
IEEE
Despite the explosive new interest in Distributed Computing, bringing software — particularly legacy software — to parallel platforms remains a daunting task. The Self Distrib...
143
Voted
SP
1999
IEEE
15 years 10 months ago
1999
IEEE
A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design ...
188
Voted
ISCAPDCS
2003
15 years 7 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
201
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ASPLOS
2000
ACM
15 years 10 months ago
2000
ACM
This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years,...
148
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ICPP
2008
IEEE
16 years 18 days ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...