13 search results - page 3 / 3 » Power-aware FPGA logic synthesis using binary decision diagr... |
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
ISCAS
2006
IEEE
14 years 8 days ago
2006
IEEE
— Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synt...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...