5 search results - page 1 / 1 » Power-aware NoC Reuse on the Testing of Core-based Systems |
79
Voted
ITC
2003
IEEE
15 years 5 months ago
2003
IEEE
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously prop...
112
click to vote
SBCCI
2003
ACM
15 years 5 months ago
2003
ACM
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
SBCCI
2004
ACM
15 years 5 months ago
2004
ACM
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
102
Voted
DAC
1998
ACM
16 years 1 months ago
1998
ACM
The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by domin...
94
Voted
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this m...