21 search results - page 2 / 5 » Power-driven Design of Router Microarchitectures in On-chip ... |
NOCS
2008
IEEE
15 years 4 months ago
2008
IEEE
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
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DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
IEEEPACT
2009
IEEE
15 years 4 months ago
2009
IEEE
—Oblivious routing can be implemented on simple router hardware, but network performance suffers when routes become congested. Adaptive routing attempts to avoid hot spots by re-...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
TC
2008
14 years 9 months ago
2008
On-chip networks (OCNs) have been proposed to solve the increasing scale and complexity of the designs in nanoscale multicore VLSI designs. The concept of irregular meshes is an im...