— With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems....
- This paper addresses the problem of maximizing capacity utilization of the battery power source in a portable electronic system under latency and loss rate constraints. First, a ...
Polymorphic electronics provides a new way for obtaining circuits that are able to perform two or more functions depending on the environment in which they operate. These function...
This paper presented a hierarchical power management architecture which aims to facilitate power-awareness in an Energy-Managed Computer (EMC) system with multiple components. The...
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...