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ICCAD
2000
IEEE
169views Hardware» more  ICCAD 2000»
15 years 1 months ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...
90
Voted
ICDCSW
2005
IEEE
15 years 3 months ago
Framework and Rule-Based Language for Facilitating Context-Aware Computing Using Information Appliances
Recently, context-aware computing with information appliances is the topic of many research efforts. In order to realize context-aware systems, it is necessary to describe rules, ...
Kouji Nishigaki, Keiichi Yasumoto, Naoki Shibata, ...
DAC
2008
ACM
15 years 10 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada
PPDP
2001
Springer
15 years 1 months ago
Constructor-Based Conditional Narrowing
We define a transformation from a left-linear constructor-based conditional rewrite system into an overlapping inductively sequential rewrite system. This transformation is sound...
Sergio Antoy
DAC
2009
ACM
15 years 10 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo