A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...
Recently, context-aware computing with information appliances is the topic of many research efforts. In order to realize context-aware systems, it is necessary to describe rules, ...
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
We define a transformation from a left-linear constructor-based conditional rewrite system into an overlapping inductively sequential rewrite system. This transformation is sound...
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...